Modern circuit designs incorporate methods and hardware that enable testing of an integrated circuit (IC) upon completion of production. Circuit designers refer to this as design for test (DFT) or design for testability. Upon completion of the IC product, IC testers apply manufacturing tests utilizing the methods and hardware included in the DFT design process. In this manner, IC testers validate that the IC hardware contains no defects that could prevent the IC from functioning as intended.
One DFT technique utilizes scan chains. Scan chains provide a simple way to set and observe every flip-flop in an IC. In order to utilize a scan chain, designers add a special signal called scan enable to an IC design. When the testing process asserts the scan enable signal, every flip-flop in the design connects into a long shift register or scan chain. One input pin provides data to this scan chain, and one output pin connects to the output of the scan chain. Using the chip's clock signal, a pre-determined pattern is entered into the chain of flip-flops, and upon completion of the test, a testing module reads out the state of every flip-flop.
The patterns entered into a scan chain are called test patterns. The state of every flip-flop upon completion of the test is generally referred to as the results or resultant pattern of the test. The testing system compares the results shifted out from the output pins against the expected “good machine” results. Good machine results are the bit patterns that are expected when the IC performed properly. In the event that the results pattern matches or compares to the good machine pattern, the IC performed in the designed manner. In the event that the good machine pattern does not match or miscompares, the IC did not perform in the designed manner, i.e., failed. When an IC test has failed, the unit conducting the test reports that a problem has been found with the IC.
Utilization of scan chains within an IC increases testability and the ability to observe the IC. However, while the scan chain diagnostic method determines when an IC has failed, scan chain diagnostics suffer particular problems when the failure occurs within a delay/buffer chain between flip-flops. Therefore, there is a need for a system and/or method for diagnosing failures within an IC that generally locates the failure and more particularly locates the failures that occur within a delay/buffer chain.